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Researchers at Tokyo Institute of Technology (Tokyo Tech) announce a Bluetooth Low-Energy transceiver with the lowest ever power consumption — a breakthrough set to accelerate widespread adoption of Internet of Things (IoT) applications in Japan and around the globe.
Figure: A photograph of the chip. The chip was designed using standard 65-nanometer CMOS technology.
An ultra-low-power Bluetooth Low-Energy transceiver designed for use in the popular 2.4 GHz band has been developed by a group of researchers led by Kenichi Okada of Tokyo Institute of Technology, Japan.
When transmitting, the transceiver consumes 2.9 milliwatts (mW) and when receiving, it consumes just 2.3 mW. Given that minimizing power consumption is a requirement for the oncoming IoT era, these figures are remarkable, as they represent less than half the power consumed by previous transceivers.
Why BLE matters
Within the next decade, IoT is projected to become a multi-trillion US dollar industry. Bluetooth Low-Energy (BLE) is in the spotlight as a key technology spurring the growth of this fast-evolving market. Already embedded in millions of Apple and Android devices, BLE is the most used short-range wireless technology aimed at low-power and low-cost connectivity.
Low-energy solutions are in demand not only for smartphones and watches, but also for emerging applications in the medical and healthcare fields, factories and public infrastructure such as roads, bridges and tunnels. IoT sensors for early detection and warning systems could mean the difference between life and death.
"Our research grew out of this need for connectivity," explains Okada. "In an IoT world, trillions of devices will be used. To extend battery life and aim for maintenance-free operations, reducing power consumption is vital."
The BLE transceiver has excellent receiver sensitivity and high interference tolerance, while also realizing the lowest power consumption.
The transmitter employs an all-digital phase-locked loop (ADPLL), an attractive building block for BLE, as it is less susceptible to noise compared to its analog counterpart. The transceiver was designed in a 65-nanometer CMOS process.
In another study focusing on ADPLL, the researchers achieved a figure of merit (FoM)4 of -246 dB, one of the best obtained so far. The FoM is an important metric for evaluating the trade-off between performance and power consumption.
The above results arose from a project supported by Japan's New Energy and Industrial Technology Development Organization (NEDO).
In future, Okada says: "The PLL could operate on just 0.65 mW, and studies are underway to reduce our transceiver's power consumption even further."
The team will present their findings at the 2018 International Solid-State Circuits Conference (ISSCC). Held every February in San Francisco, the conference, popularly known as the Chip Olympics, is regarded as the leading forum on integrated circuit research and development.