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Semiconductor startup Tachyum Inc. announced today that it has achieved, on schedule, a major milestone in the detailed physical design of its Prodigy Universal Processor. Tachyum now has a complete chip layout, with a verified detailed physical design of more than 90% of the design silicon area.
Tachyum’s Prodigy is the world’s first Universal Processor, combining general-purpose processors, high-performance computing (HPC), artificial intelligence (AI), deep machine learning (ML), explainable AI, bio AI and other AI disciplines within a single chip. This latest milestone achieved integration of key, high-quality Tachyum IP within a multiprocessor environment, and with DDR4/DDR5 DRAM controllers, PCIE 5.0, 112Gb SERDES, USB, GPIO, PLLs and various I/Os. Results of the layout indicate that Prodigy’s die size is within product design goals with top-level clocking results that are better than expected.
“Next-generation leading-edge AI CPU SoCs need to integrate high-performance IP solutions that meet a range of specialized processing, memory performance and real-time data connectivity design requirements inclusive of high-speed 112G PAM4 SerDes,” said Rishi Chugh, vice president of product marketing, IP Group at Cadence. “Cadence’s best-in-class IP portfolio solutions are silicon proven in advanced process nodes and deliver optimal design productivity, enabling Tachyum to accelerate their development cycle and differentiate in the fast-moving AI market.”
“With die size and clock speed both being on target, we are confident in our ability to deliver the world’s first universal processor. It will radically improve compute performance and efficiency for data center, AI and HPC workloads,” said Tachyum CEO Dr. Radoslav Danilak.
Prodigy, the company’s 64-core flagship product, is scheduled for high-rate production in 2021. It outperforms the fastest Xeon processors at 10x lower power (core vs. core) on data center workloads, as well as outperforming NVIDIA’s fastest GPU on neural net AI training and inference. Due to its high computational density and I/O bandwidth, networks of Prodigy processors comprising of just 125 HPC racks, can deliver an ExaFLOPS (a billion, billion floating point operations per second) of capacity. Prodigy’s 3X lower cost per MIPS, compared to other CPU competition, coupled with its 10X processor power savings translates to a 4X reduction in Data Center TCO (Annual Total Cost of Ownership: CAPEX + OPEX). Even at 50% Prodigy attach rates, this translates to billions of dollars per year in real savings for hyperscalers such as Google, Facebook, and Amazon.
Since Prodigy can seamlessly and dynamically switch from data center workloads to AI or HPC workloads, unused servers can be powered up, on demand, as ad hoc AI or HPC networks—CAPEX free, since the servers themselves are already purchased. Every Prodigy-provisioned data center, by definition, becomes a low-cost AI center of excellence, and a low-cost HPC system.