Synopsys Broadens Collaboration with EPFL


Reading time ( words)

Synopsys, Inc. announced it has broadened its ongoing academic collaboration by entering into an agreement to license novel digital synthesis technologies from EPFL, the Swiss Federal Institute of Technology in Lausanne, Switzerland.

Over the past two years, Synopsys has been working in partnership with the University of Rochester and Yokohama National University developing a complete digital circuit design flow for Superconducting Electronics (SCE). This work is being conducted under IARPA's SuperTools project, a multi-year research effort that aims to create a SCE circuit design flow by developing a comprehensive set of Electronic Design Automation (EDA), and Technology Computer Aided Design (TCAD) tools to enable the analysis and design of SCE circuits with Very-Large-Scale Integration (VLSI).

EPFL's Integrated Systems Laboratory (LSI) has developed a method that may reduce the power requirement of electronic chips by mapping out their logic flows in a novel way. By deploying a different set of logic functions for the gates on the potentially billions of transistors found in modern electronic circuits, this system may shorten the circuits' calculation steps. This shortening may enable chip designers to make their chips faster or more energy efficient. EPFL's LSI is applying these methods in ongoing research on SCE conducted under NSF's SuperCool project.

Traditionally, four basic logic functions (and-or-not-mux) have been used to realize electronic circuits. But, EPFL's LSI group set out to produce optimized digital circuits by radically changing the software that generates logic diagrams involving majority functions. Initial studies indicated that the new approach could reduce the number of logic steps needed to execute a given task. Later experiments confirmed that these optimizations were able to reduce the number of logic levels by 18% on average. Engineers can exploit the reduction in logic levels to create faster or less power-hungry chips.

The SCE tools will allow engineers to design complex, high-speed digital circuits with much lower power requirements than available in today's semiconductor technologies. Advanced EDA and TCAD tools have been at the center of the semiconductor revolution and made possible the design and manufacture of today's highly sophisticated electronic systems. The SuperTools project endeavors to apply the experiences and learnings from semiconductors to superconducting electronics, offering the possibility of faster circuits with substantially lower power requirements.

Share

Print


Suggested Items

Kirigami Inspires New Method for Wearable Sensors

10/22/2019 | University of Illinois
As wearable sensors become more prevalent, the need for a material resistant to damage from the stress and strains of the human body’s natural movement becomes ever more crucial. To that end, researchers at the University of Illinois at Urbana-Champaign have developed a method of adopting kirigami architectures to help materials become more strain tolerant and more adaptable to movement.

Worldwide Semiconductor Equipment Billings at $13.3 Billion in 2Q19; Down 20%

09/12/2019 | SEMI
Worldwide semiconductor manufacturing equipment billings reached $13.3 billion in the second quarter of 2019, down 20% from the same quarter of 2018 and 3% from than the previous quarter.

Designing Chips for Real Time Machine Learning

04/01/2019 | DARPA
DARPA’s Real Time Machine Learning (RTML) program seeks to reduce the design costs associated with developing ASICs tailored for emerging ML applications by developing a means of automatically generating novel chip designs based on ML frameworks.



Copyright © 2020 I-Connect007. All rights reserved.