Lightmatter’s Optical Processor to Speed Compute for Next-Generation AI


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Lightmatter, a leader in silicon photonics processors, announces its artificial intelligence (AI) photonic processor, a general-purpose AI inference accelerator that uses light to compute and transport data. Using light to calculate and communicate within the chip reduces heat—leading to orders of magnitude reduction in energy consumption per chip and dramatic improvements in processor speed.

Since 2010, the amount of compute power needed to train a state-of-the-art AI algorithm has grown at five times the rate of Moore’s Law scaling—doubling approximately every three and a half months. Lightmatter’s processor solves the growing need for computation to support next-generation AI algorithms.

“The Department of Energy estimates that by 2030, computing and communications technology will consume more than 8 percent of the world’s power. Transistors, the workhorse of traditional processors, aren’t improving; they’re simply too hot. Building larger and larger datacenters is a dead end path along the road of computational progress,” said Nicholas Harris, PhD, founder and CEO at Lightmatter. “We need a new computing paradigm. Lightmatter’s optical processors are dramatically faster and more energy efficient than traditional processors. We’re simultaneously enabling the growth of computing and reducing its impact on our planet.”

On August 18th, Lightmatter’s VP of Engineering, Carl Ramey, will present their photonic processor architecture at HotChips32. The 3D-stacked chip package contains over a billion FinFET transistors, tens of thousands of photonic arithmetic units, and hundreds of record-setting data converters. Lightmatter’s photonic processor runs standard machine learning frameworks including PyTorch and TensorFlow, enabling state-of-the-art AI algorithms.

This new architecture is a massive advancement in the development of photonic processors. The performance of this photonic processor provides proof that Lightmatter’s approach to processor design delivers scalable speed and energy efficiency advantages over the current electronic compute paradigm and is the starting point for a roadmap of chips with dramatic performance improvements.

 

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