Cadence Releases UltraLink D2D PHY IP on TSMC N7, N6 and N5 Processes

Reading time ( words)

Cadence Design Systems, Inc. announced the availability of its silicon-proven Cadence® UltraLink D2D PHY IP on the TSMC N7 process. Test silicon on the TSMC N7 process with full silicon characterization data is now available, an important milestone for very high-speed, advanced IP. Extensive silicon validation is necessary to guarantee design margins, performance across all process corners, bit-error rate (BER), insertion loss and maximum transmission speed. For the N6 process, re-characterized silicon data is available. Cadence is ready to engage with customers now with its UltraLink D2D PHY IP on the TSMC N7 and N6 processes. Cadence also recently taped out its UltraLink D2D IP on the TSMC N5 process and is now working with early adopter customers ahead of anticipated test silicon availability later this year.

System advances in accelerated computing platforms such as CPUs, GPUs and FPGAs, heterogeneous systems on chip (SoCs) for AI acceleration and high-speed networking/interconnects have all pushed chip integration to unprecedented levels. This requires more complex designs, larger die sizes and rapid adoption of the most advanced geometries. In order to manage the economics of advanced silicon and the ever-increasing monolithic die size, die-to-die connectivity has become increasingly important as multi-die designs using advanced packaging have become quite common.

“We’re pleased to see the result of our latest collaboration with Cadence in delivering Cadence’s D2D PHY IP across several TSMC advanced processes,” said Suk Lee, senior director of the Design Infrastructure Management Division at TSMC. “This joint effort combining Cadence’s leading-edge SerDes IP and TSMC’s advanced process technologies helps our customers unleash their silicon innovations for emerging cloud computing, AI, 5G and hyperscale data center applications.”

“To help our mutual customers achieve success in advanced SoC designs for cloud computing applications, we’ve enabled our UltraLink D2D PHY IP in multiple TSMC advanced processes: First in N7 and N6, with a quick follow-on with N5 later this year,” said Rishi Chugh, vice president of product marketing, IP Group at Cadence. “To address our customers’ rapidly evolving requirements, we continue to invest in both PAM4 and NRZ SerDes IP. The UltraLink D2D PHY IP is a critical technology delivering high bandwidth, low latency and power while enabling the proliferation of heterogeneous designs and integrated packaging solutions.”

The UltraLink D2D PHY IP delivers up to 40Gbps wire speed in an NRZ serial interface, providing up to 1Tbps/mm unidirectional bandwidth. While some existing lower speed die-to-die solutions require a silicon interposer to achieve the same bandwidth, the UltraLink D2D PHY IP offers significant cost advantages by supporting multi-chip modules on organic substrates. The IP extends Cadence’s broad high-performance computing (HPC) IP portfolio in support of the company’s Intelligent System Design strategy, enabling SoC design excellence. 



Suggested Items

Kirigami Inspires New Method for Wearable Sensors

10/22/2019 | University of Illinois
As wearable sensors become more prevalent, the need for a material resistant to damage from the stress and strains of the human body’s natural movement becomes ever more crucial. To that end, researchers at the University of Illinois at Urbana-Champaign have developed a method of adopting kirigami architectures to help materials become more strain tolerant and more adaptable to movement.

Worldwide Semiconductor Equipment Billings at $13.3 Billion in 2Q19; Down 20%

09/12/2019 | SEMI
Worldwide semiconductor manufacturing equipment billings reached $13.3 billion in the second quarter of 2019, down 20% from the same quarter of 2018 and 3% from than the previous quarter.

Designing Chips for Real Time Machine Learning

04/01/2019 | DARPA
DARPA’s Real Time Machine Learning (RTML) program seeks to reduce the design costs associated with developing ASICs tailored for emerging ML applications by developing a means of automatically generating novel chip designs based on ML frameworks.

Copyright © 2021 I-Connect007. All rights reserved.