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Cadence Design Systems, Inc. announced that its digital and custom/analog flows have achieved certification for TSMC’s N3 and N4 process technologies in support of the latest Design Rule Manual (DRM). Through continued collaborations, Cadence and TSMC delivered the corresponding process design kits (PDKs) for TSMC N3 and N4 processes to accelerate mobile, AI and hyperscale computing innovation. In addition, mutual customers have already validated the benefits of the Cadence® flows and TSMC’s process technologies through successful tapeouts.
N3 and N4 Digital Flow Certifications
Cadence worked closely with TSMC to optimize the digital flow for TSMC’s advanced N3 and N4 process technologies to help customers achieve power, performance and area (PPA) goals and speed time to market. The complete, integrated RTL-to-GDS flow includes the Cadence Innovus™ Implementation System, Liberate™ Characterization Solution, Quantus™ Extraction Solution, Quantus Field Solver, Tempus™ Timing Signoff Solution and ECO Option, and the Voltus™ IC Power Integrity Solution. Additionally, the Cadence Genus™ Synthesis Solution and predictive iSpatial technology are enabled for the N3 and N4 process technologies.
The digital full flow enables customers to successfully design on TSMC’s N3 and N4 process technologies through several capabilities, including:
- Efficient processing of large libraries: Among the variations of threshold voltage and drive strength, the Cadence flow efficiently processes these large libraries, ensuring the best run-time for increasingly complex designs.
- Timing analysis accuracy: N3 requires additional accuracy during library cell characterization and static timing analysis (STA). The Cadence flow has been enhanced to address all N3 timing characterization and signoff requirements.
- Accurate power signoff: Support for accurate leakage calculation required in N3 and static power calculation for new N3 cells has been added. N3 power calculation accuracy, which included different power components—switching, internal, and leakage, for example—has been validated at multiple corners, temperatures and voltages. The Cadence flow meets all N3 power signoff requirements.
N3 and N4 Custom/Analog Tool Suite Certification
Cadence has continued its long-standing collaboration with TSMC engineers to deliver a comprehensive custom, analog, EM-IR and mixed-signal design solution, addressing the challenges and complexities for designing custom and analog IP in TSMC’s N3 and N4 process technologies. Through this collaboration, the Virtuoso® Design Platform, Spectre® Simulation Platform and the Voltus-Fi Custom Power Integrity Solution have achieved the latest TSMC N3 and N4 PDK requirements.
The custom flow for N3 and N4 process technologies make use of the following design solutions:
- Spectre Simulation Platform: Offers comprehensive time- and frequency-domain analyses capabilities, including AC, DC and transient simulations with an emphasis on managing large device and interconnect parasitic networks, harmonic-balancing, noise analysis and EM-IR with the Voltus-Fi Custom Power Integrity Solution.
- Virtuoso Schematic Editor: Provides design capturing and drives the Virtuoso Layout Suite for Schematic-Driven Layout.
- Virtuoso ADE Suite: Integrates with the Spectre X Simulator to effectively manage corner simulations, statistical analyses, design centering and circuit optimization.
- Virtuoso Layout Suite EXL: Offers an advanced layout environment for efficient layout implementation, which leverages a unique row-based implementation methodology with interactive, assisted features for placement, routing, fill and dummy insertion.
- Mixed-signal implementation flow: Provides a tight integration between the Virtuoso Design Platform and the Innovus Implementation System, improving engineering productivity through an enhanced implementation methodology for mixed-signal designs using a common mixed-signal open access database.
In addition, the Virtuoso and Spectre platforms have been certified for TSMC’s N3 and N4 process technologies.
“Through our continued collaboration with Cadence, we’re enabling customers to improve productivity with certified flows for our advanced N3 and N4 process technologies,” said Suk Lee, vice president of the Design Infrastructure Management Division at TSMC. “This joint effort between TSMC and Cadence is making it easy for customers who are creating next-generation mobile, AI and hyperscale computing designs to achieve PPA goals and quickly launch their differentiated products to market.”
“By working closely with TSMC, our customers have access to the most sophisticated capabilities to create competitive designs with TSMC’s N3 and N4 process technologies and our digital flow and custom/analog flow,” said Dr. Chin-Chi Teng, senior vice president and general manager in the Digital & Signoff Group at Cadence. “We continuously listen to our mutual customers to gain an understanding of their real-world design requirements, and their feedback enabled us to tailor our flows accordingly so they can achieve SoC design excellence.”