Cadence Design IP Portfolio in TSMC’s N5 Process Gains Broad Adoption Among Leading Semiconductor, System Companies
June 16, 2022 | Cadence Design Systems, Inc.Estimated reading time: 1 minute
Cadence Design Systems, Inc. announced a wide range of leading semiconductor and system customers have successfully adopted the comprehensive line-up of Cadence® Design IP in TSMC’s industry-leading 5nm process technology. Designed to the latest state-of-the-art interface standards, the Cadence’s Design IP portfolio enables customers to develop the most advanced SoCs for the most demanding applications, including high-performance computing (HPC), artificial intelligence/machine learning (AI/ML), networking, storage, and automotive. The IP portfolio from Cadence in TSMC’s N5 process includes 112/56/25/10 Gbps Ethernet PHY/MAC, PCIe 6.0/5.0/4.0/3.1 PHY/Controller, 40Gbps Ultralink™ D2D PHY, and complete PHY/Controller for GDDR6, DDR5/4, and LPDDR5/4x.
Cadence’s design IP in TSMC’s N5 process delivers optimal power, performance and area (PPA) with rich feature sets to enable uncompromised differentiation, versatility and innovation for large-scale SoC designs. In addition, Cadence provides full subsystem deliveries with integrated PHY and controller IP to simplify integration, minimize risks, and enable faster time to market.
“TSMC worked closely with Cadence, our long-standing ecosystem partner, to enable leading-edge designs, which deliver significant power, performance and area improvements on our advanced technologies,” said Suk Lee, vice president of the Design Infrastructure Management Division at TSMC. “The strong collaboration between Cadence’s Design IP and TSMC’s IP9000 teams promotes high-quality IP delivery to help our mutual customers achieve first-pass silicon success and faster time-to-market.
"Cadence has collaborated with TSMC for decades to provide high-quality silicon-proven IP on advanced process nodes to meet the most demanding requirements for HPC, AI/ML, networking, storage, and automotive applications,” said Rishi Chugh, vice president of Design IP Product Management at Cadence. "The wide adoption of our Design IP in TSMC’s N5 process demonstrates the excellence and quality of Cadence’s Design IP, which is empowering customers to design highly differentiated product solutions.”
Suggested Items
Elevating PCB Design Engineering With IPC Programs
04/24/2024 | Cory Blaylock, IPCIn a monumental stride for the electronics manufacturing industry, IPC has successfully championed the recognition of the PCB Design Engineer as an official occupation by the U.S. Department of Labor (DOL). This pivotal achievement not only underscores the critical role of PCB design engineers within the technology landscape, but also marks the beginning of a transformative journey toward nurturing a robust, skilled workforce ready to propel our industry into the future.
IPC Design Competition Champion Crowned at IPC APEX EXPO 2024
04/24/2024 | IPCAt IPC APEX EXPO 2024 in Anaheim, California, five competitors squared off to determine who was the best of the best at PCB design.
Altus Group Helps BitBox Unlock Productivity and Efficiency Gains with New Reflow Oven
04/22/2024 | Altus GroupAltus Group, a leading provider of capital equipment, has recently assisted BitBox, a UK-based electronics design, engineering and manufacturing company in upgrading its operations with the implementation of a new reflow oven from Heller Industries.
Real Time with... IPC APEX EXPO 2024: Exploring IPC's PCB Design Courses with Kris Moyer
04/18/2024 | Real Time with...IPC APEX EXPOGuest Editor Kelly Dack and IPC instructor Kris Moyer discuss IPC's PCB design training and education offerings. They delve into course topics such as design fundamentals, mil/aero, rigid-flex, RF design, and advanced design concepts. They also highlight material selection for high-speed design, thermal management, and dissipation techniques. The interview wraps up with details about how to access these courses online.
Cadence Unveils Palladium Z3 and Protium X3 Systems
04/18/2024 | Cadence Design SystemsThe Palladium Z3 and Protium X3 systems offer increased capacity, and scale from job sizes of 16 million gates up to 48 billion gates, so the largest SoCs can be tested as a whole rather than just partial models, ensuring proper functionality and performance.