Cadence Design IP Portfolio in TSMC’s N5 Process Gains Broad Adoption Among Leading Semiconductor, System Companies
June 16, 2022 | Cadence Design Systems, Inc.Estimated reading time: 1 minute
Cadence Design Systems, Inc. announced a wide range of leading semiconductor and system customers have successfully adopted the comprehensive line-up of Cadence® Design IP in TSMC’s industry-leading 5nm process technology. Designed to the latest state-of-the-art interface standards, the Cadence’s Design IP portfolio enables customers to develop the most advanced SoCs for the most demanding applications, including high-performance computing (HPC), artificial intelligence/machine learning (AI/ML), networking, storage, and automotive. The IP portfolio from Cadence in TSMC’s N5 process includes 112/56/25/10 Gbps Ethernet PHY/MAC, PCIe 6.0/5.0/4.0/3.1 PHY/Controller, 40Gbps Ultralink™ D2D PHY, and complete PHY/Controller for GDDR6, DDR5/4, and LPDDR5/4x.
Cadence’s design IP in TSMC’s N5 process delivers optimal power, performance and area (PPA) with rich feature sets to enable uncompromised differentiation, versatility and innovation for large-scale SoC designs. In addition, Cadence provides full subsystem deliveries with integrated PHY and controller IP to simplify integration, minimize risks, and enable faster time to market.
“TSMC worked closely with Cadence, our long-standing ecosystem partner, to enable leading-edge designs, which deliver significant power, performance and area improvements on our advanced technologies,” said Suk Lee, vice president of the Design Infrastructure Management Division at TSMC. “The strong collaboration between Cadence’s Design IP and TSMC’s IP9000 teams promotes high-quality IP delivery to help our mutual customers achieve first-pass silicon success and faster time-to-market.
"Cadence has collaborated with TSMC for decades to provide high-quality silicon-proven IP on advanced process nodes to meet the most demanding requirements for HPC, AI/ML, networking, storage, and automotive applications,” said Rishi Chugh, vice president of Design IP Product Management at Cadence. "The wide adoption of our Design IP in TSMC’s N5 process demonstrates the excellence and quality of Cadence’s Design IP, which is empowering customers to design highly differentiated product solutions.”
Suggested Items
iNEMI Packaging Tech Topic Series: Role of EDA in Advanced Semiconductor Packaging
04/26/2024 | iNEMIAdvanced semiconductor packaging with heterogenous integration has made on-package integration of multiple chips a crucial part of finding alternatives to transistor scaling. Historically, EDA tools for front-end and back-end design have evolved separately; however, design complexity and the increased number of die-to-die or die-to-substrate interconnections has led to the need for EDA tools that can support integration of overall design planning, implementation, and system analysis in a single cockpit.
Cadence, TSMC Collaborate on Wide-Ranging Innovations to Transform System and Semiconductor Design
04/25/2024 | Cadence Design SystemsCadence Design Systems, Inc. and TSMC have extended their longstanding collaboration by announcing a broad range of innovative technology advancements to accelerate design, including developments ranging from 3D-IC and advanced process nodes to design IP and photonics.
Ansys, TSMC Enable a Multiphysics Platform for Optics and Photonics, Addressing Needs of AI, HPC Silicon Systems
04/25/2024 | PRNewswireAnsys announced a collaboration with TSMC on multiphysics software for TSMC's Compact Universal Photonic Engines (COUPE). COUPE is a cutting-edge Silicon Photonics (SiPh) integration system and Co-Packaged Optics platform that mitigates coupling loss while significantly accelerating chip-to-chip and machine-to-machine communication.
Siemens’ Breakthrough Veloce CS Transforms Emulation and Prototyping with Three Novel Products
04/24/2024 | Siemens Digital Industries SoftwareSiemens Digital Industries Software launched the Veloce™ CS hardware-assisted verification and validation system. In a first for the EDA (Electronic Design Automation) industry, Veloce CS incorporates hardware emulation, enterprise prototyping and software prototyping and is built on two highly advanced integrated circuits (ICs) – Siemens’ new, purpose-built Crystal accelerator chip for emulation and the AMD Versal™ Premium VP1902 FPGA adaptive SoC (System-on-a-chip) for enterprise and software prototyping.
Listen Up! The Intricacies of PCB Drilling Detailed in New Podcast Episode
04/25/2024 | I-Connect007In episode 5 of the podcast series, On the Line With: Designing for Reality, Nolan Johnson and Matt Stevenson continue down the manufacturing process, this time focusing on the post-lamination drilling process for PCBs. Matt and Nolan delve into the intricacies of the PCB drilling process, highlighting the importance of hole quality, drill parameters, and design optimization to ensure smooth manufacturing. The conversation covers topics such as drill bit sizes, aspect ratios, vias, challenges in drilling, and ways to enhance efficiency in the drilling department.