Cadence Introduces Industry’s Leading-Performance, Silicon-Proven 22Gbps GDDR6 IP at TSMC N5


Reading time ( words)

Cadence Design Systems, Inc. announced that Cadence IP for GDDR6 is silicon proven on TSMC’s N5 process technology, exceeding Cadence’s previous 16Gbps designs. Targeted for very high-bandwidth memory applications, including hyperscale computing, 5G communications, automotive and consumer, the GDDR6 IP consists of Cadence PHY and controller design IP and Verification IP (VIP). GDDR6 is particularly well suited for the memory interface in artificial intelligence/machine learning (AI/ML) chips, which are proliferating due to the growing number of AI inferencing applications. Customers can speed development and reduce risk when using Cadence and TSMC technologies to design these chips that connect to GDDR6 memory.

The Cadence IP for GDDR6 at TSMC N5 operating at 22Gbps offers more than 2X the data rate of other latest generation standards like DDR5 and LPDDR5 and is 37% faster than Cadence’s previous 16Gbps designs. An improved architecture allows up to 22Gbit/sec bandwidth per pin—704Gbit/sec per chip—across the full range of operating conditions, with low operational power and idle power as well as a low bit-error rate (BER) for higher reliability and greater bandwidth. The corresponding GDDR6 controller IP offers a variety of performance and reliability features derived from Cadence’s DDR controller designs.

“Cadence’s latest GDDR6 IP on TSMC’s N5 process technology has achieved a significant performance boost in silicon compared with Cadence’s previous solutions in TSMC N7, N6 and 12nm FinFET Compact (12FFC) processes,” said Dan Kochpatcharin, Head of Design Infrastructure Management Division at TSMC. “This result of our latest collaboration combining Cadence’s leading IP solutions with TSMC’s advanced process technology enables new chips in AI/ML, hyperscale, and other computationally intense applications.”

“Cadence is committed to expanding our IP portfolio to address our customers’ evolving design requirements. Customers can now capitalize on the higher bandwidth offered by the Cadence Design IP for GDDR6 on TSMC’s N5 process technology with the utmost confidence,” said Sanjive Agarwala, corporate vice president and general manager of the IP Group at Cadence. “The improved PHY and controller design IP for GDDR6 with DRAM data rates at 22Gbps in the TSMC N5 process is the fastest of the GDDR6 family of IP in advanced TSMC nodes.”

Share




Suggested Items

AIS, Qualcomm, ZTE Announce the World’s First 5G NR-DC Showcase for 2.6GHz and 26GHz in Thailand

04/01/2022 | Qualcomm Technologies, Inc.
AIS, Qualcomm Technologies, Inc. and ZTE announced the world’s first 5G NR-DC (New Radio Dual Connectivity) showcase in the field with 2.6GHz and 26GHz, achieving 8.5Gbps peak downlink speed and 2.17Gbps peak uplink speed with a single mobile device.

My View from CES 2021: Day 1

01/12/2021 | Dan Feinberg, Technology Editor, I-Connect007
What a difference a year makes. One year ago, those of us who cover and attend CES were going from one press conference to the next; this year, we are at home going from link to link. Confusing and challenging, yes, but there are some advantages: no masks, only five steps to get to a restroom, being able to have three of four events or more displaying on your screens at the same time and being able to download press kits as needed. So far, many new devices are being introduced, but of course, they are all online, so you wonder if some of them really exist or are truly operational as yet.

CES 2021: Just How Different Will It Be?

01/11/2021 | Dan Feinberg, I-Connect007
CES 2021 starts today and this year there is no need for an overpriced hotel room in Vegas, no long lines to get a taxi or board a bus, and no crowded exhibit halls (one good thing this year). On the other hand, you must decide ahead of time what you want to see and make a reservation or appointment if you wish to have time and access assured.



Copyright © 2022 I-Connect007 | IPC Publishing Group Inc. All rights reserved.