Over the last 35 years we have seen astonishing advances in printed circuits, flex circuits, and component technology. The introduction of surface mount technology back in the ‘80s and the continued progression of that technology has proven to be a challenge for PCB manufacturers and the electrical test arena as well.
From a development engineer standpoint, the task is to economically create the design using the best available technologies that provide the optimum result. This includes, but is not limited to, component packages, blind and buried via technology, and buried passives, while also considering the manufacturing abilities of the selected PCB fab vendor. Considerations are line width, spacing, component density, and deliverable characteristics such as TDR, HiPot, inductance, and of course, overall electrical compliance. In the early days this was never a problem as most PCBs were plated through-hole (PTH) and electrical test was straightforward. Not so much today.
Design for manufacturing (DFM) is a great discipline for creating designs that provide optimum performance while still maintaining affordability. However, what can be, and does get overlooked, is the design for test (DFT) variable. As greater manufacturing demands are put to the manufacturer, it also creates challenges to validate the electrical deliverables that may be required.
From an electrical test standpoint, the layer count of a given PCB is not an issue. The CAM systems of today can process many layers including blind/buried vias, buried passives and the like. The challenge becomes the actual test. Net intelligence is not the hurdle but how to effectively interrogate the PCB to provide validation of the electrical characteristics. Historically this has been easy.
Fixture technology and fixture testers were all the rave through the ‘80s, ‘90s, and into the new millennium. Using headed pin technology through featureless music wire allowed the successful test of most designs. Even with the higher density, the CAM systems were able to split fixtures to A and B tests to encapsulate the extremely dense PCBs. Unfortunately, this has some drawbacks. The extra fixtures and increased drilling and assembly time adds cost and time to the equation. Whether ET is captured in the quoting process by the manufacturer will be the decision of the individual manufacturer, but these costs are real in both time and materials/labor.
As today’s designs get more complex, economics come in to play as to whether fixtures are the answer. Extremely dense designs are now requiring quad-density or greater to still utilize fixture technology, or they are being converted to dedicated spring probe fixtures that are very costly. These variables are usually not considered during the quoting process (remember DFT) and can cause loss of margin by the time the electrical deliverables are met.
Now, today’s flying probe machines can test extremely dense designs without using fixtures. The cost is much less but there are trade-offs from the fixture test. Flying probes cannot provide the full parametric test that fixture testers can provide. This can be an issue when testing some military, aerospace, and high reliability medical products. These require the “simultaneous” test of the PCB for opens and more importantly, shorts. So, in some of these cases a fixture or multiple fixtures will be required. This increases cost and can cause delays in the manufacturing window due to manufacture of the fixture(s).
Where is this going? Design for test. Speaking for the ET arena, PCB designers are encouraged to take into consideration how their electrical deliverables can be met. Sure, flying probes can tackle most designs and requirements of today, including test of buried passives, HiPot, inductance, and even capacitance. However, in high-reliability products that require full parametric tests, fixtures will be required. Here is where consideration will be most beneficial. Consult with your manufacturer on electrical test density capabilities to make sure your design can be tested effectively. If your design is beyond the capability, consider adding a pad or feature to allow the effective probing of the network. Sometimes adding a small 0.010-0.015” pad, spaced appropriately for ET capability, may turn your untestable design into a routine build. This can be increasingly effective for wire-bond technology where direct probing of the wire-bond pristine area is prohibited. Doing so may stress you out a bit finding real estate to add these features for test, but usually this would not increase the price of the actual PCB build. However, it does make a significant difference in the testability of the PCB design.
While DFM is an absolute necessity in the market of today, DFT needs the attention more today than ever. An overall great design implementing DFM and DFT will make the manufacturing cycle less expensive and keep the time frame for deliverables in check. Don’t forget ET.
This column originally appeared in the August 2021 issue of PCB007 Magazine.