Sondrel Delivers Tape-out of Largest Chip Design
November 2, 2020 | SondrelEstimated reading time: 2 minutes
Sondrel has announced the tape-out of its largest chip design for a customer. This has taken a team of up to 200 engineers working on it simultaneously at times to design the 500 square millimetre chip that has over 30 billion transistors, 40 million flipflops, and 23 thousand pads for I/O, power and ground.
“This initially started out as a design for 28nm technology,” explained Stuart Vernon, Sondrel’s Senior Director of Physical Design. “However, it soon became apparent that, on 28nm, it would either be one very big chip, which would not have been cost effective, or it would have to be split into two connected chips, which would introduce parasitics and timing issues. So the decision was made to use the 16nm TSMC process node to enable the design to fit onto a single chip at a cost effective price point.”
Around a third of the floor plan of the chip is the block with the customer’s IP that handles the real-time image processing. Sondrel wrapped round that support blocks of Graphical Processor Unit, two Central Processor Units, on-chip cache memory, PCI and USB interfaces plus memory controllers to off-chip memory using over 7 kilometres of metal tracks on a chip the size of a postage stamp.
It would be impossible to design a chip of this complexity in one go as it has 300 million placeable logic cells and the placement tool can only handle 3 million at a time without the runtime becoming excessive. It was therefore divided into manageable-sized, functional blocks over four levels of a hierarchy structured like a pyramid. This enabled the design of the blocks to be divided between Sondrel teams that are located around the world. Once each block was finished, the big challenge was to bring them all together by creating abstract models of the lower blocks to provide input for the higher blocks so that the size of the part of design being implemented remained manageable. As the chip can run at up to 100 Watts, even the heat output of the different parts of the chip have to be allowed for in the design to prevent hotspots
Once all the component blocks had been implemented, the whole design was run as a complete unit on a dedicated computer farm consisting of 25 computers, each with 24 CPUs and 1.5 Terabytes of memory, and over 100 software licenses to perform physical validation checks, which took two days.
“We are one of the few digital design companies that can handle a design of this size and complexity, and we have several more nearing completion,” said Graham Curran, Sondrel’s CEO and Founder. “A key part of this is our experience of managing the logistics of having teams in seven different locations and co-ordinating their work. For example, our teams in India and China work in the evenings to maximise the overlap with our teams in Europe.”
Suggested Items
Altus Group Helps BitBox Unlock Productivity and Efficiency Gains with New Reflow Oven
04/22/2024 | Altus GroupAltus Group, a leading provider of capital equipment, has recently assisted BitBox, a UK-based electronics design, engineering and manufacturing company in upgrading its operations with the implementation of a new reflow oven from Heller Industries.
Real Time with... IPC APEX EXPO 2024: Exploring IPC's PCB Design Courses with Kris Moyer
04/18/2024 | Real Time with...IPC APEX EXPOGuest Editor Kelly Dack and IPC instructor Kris Moyer discuss IPC's PCB design training and education offerings. They delve into course topics such as design fundamentals, mil/aero, rigid-flex, RF design, and advanced design concepts. They also highlight material selection for high-speed design, thermal management, and dissipation techniques. The interview wraps up with details about how to access these courses online.
Cadence Unveils Palladium Z3 and Protium X3 Systems
04/18/2024 | Cadence Design SystemsThe Palladium Z3 and Protium X3 systems offer increased capacity, and scale from job sizes of 16 million gates up to 48 billion gates, so the largest SoCs can be tested as a whole rather than just partial models, ensuring proper functionality and performance.
Signal Integrity Expert Donald Telian to Teach 'Signal Integrity, In Practice' Masterclass Globally
04/17/2024 | PRLOGDonald Telian and The EEcosystem announce the global tour of "Signal Integrity, In Practice," a groundbreaking LIVE masterclass designed to equip hardware engineers with essential skills for solving Signal Integrity (SI) challenges in today's fast-paced technological landscape.
On the Line With... Podcast Talks With Cadence Expert on Manufacturing
04/18/2024 | I-Connect007In “PCB 3.0: A New Design Methodology: Manufacturing” Patrick Davis returns to the podcast to talk about design rules. As design considerations become more and more complex, so, too, do the rulesets designers must abide by.