Reading time ( words)
Chapter 2: Challenges in Design and Development of Electronic Systems
The exponential growth in data center infrastructure for IT networking introduced numerous challenges, from limited ecosystems to high-performance computing issues. There are many constraints on building data centers and updating the equipment in them. Planning is critical in managing increased capacity in the existing data center space. Increased rack density disturbs the prevailing power distribution infrastructure. When more devices are added to the existing space, temperature increases, and the need for containment solutions and precision cooling arises. Also, the components must be able to handle higher temperatures. Managing load capacity/phase power and weight of the equipment is another challenge. In addition, racks also have energy efficiency issues, and rack depth can cause incompatibility with newer designs. While other challenges in the context of hardware and software exist—like advanced node implementation at 7nm and verification of complex domain-specific architectures—this section focuses mainly on system analysis aspects. Data centers require high-computing devices in small footprints. With a decrease in transistor size, an advanced node is created. Small form factor brings several gains like higher density and faster switching. However, at the same time, advanced nodes take the design and integration complexity to a new level
Decreasing metal pitch leads to coupling effects and signal integrity issues. Increasing wire and via resistance requires more advanced and variable wire sizing and tapering techniques to compensate. Server signals, chip complexity and cost, power management and electromigration, achieving performance goals, lithography limitations, process complexity and variability in extraction, timing, signal integrity analysis, and modeling, package complexity, shorter time-to-market, and project management (engineers/project cost) are some of the critical challenges in advanced node chip design.
The advanced node creates chip layout design challenges due to irregular layout that causes routing congestion. Also, wide buses used for inter-block communication in the chip increase congestion. While manufacturing, advanced nodes face lithography, process, and packaging issues. And due to the use of high-K metal gates (HKMGs) and silicon-on-insulator (SoI) technology, foundry rules present relatively new complications. The use of stress-and-strain engineering causes varying electrical effects that depend on layout features. Rule-based metal fill does not consider multilayer effects and so may cause varying results. Double-patterning technology has its ecosystem of issues. Besides, due to the increased complexity in lithography, conventional model-based optical proximity correction (OPC) and resolution enhancement techniques (RETs) are not enough to deliver the required silicon pattern fidelity. Packaging issues may include thermal and stress challenges due to die disaggregation, 3D stacking (3D-ICs), and TSVs. Interdependency challenges are not easy to manage. A chip’s electrical properties vary with lithography, and process and packaging details vary depending on the chip’s layout. From floor planning to signoff, tools must interact to make countless adjustments and tradeoffs.
To download this free eBook, published by I-Connect007, click here.
To view the entire I-Connect007 eBook library, click here.