Cadence Cerebrus Delivers Transformative Results on Next-Gen Designs


Reading time ( words)

Cadence Design Systems announced that customer adoption of the Cadence Cerebrus Intelligent Chip Explorer is accelerating with new production deployments completed. Given that Cadence Cerebrus employs artificial intelligence (AI) technology to automate and scale digital chip design, it offers customers the compelling value proposition of optimized power, performance and area (PPA) and improved engineering productivity.

Cadence Cerebrus is a transformational AI-driven technology that has a unique reinforcement learning engine, which automatically optimizes tool and chip design options to deliver better PPA with significantly less engineering effort and overall time to tapeout. As one example, the Cadence Cerebrus floorplan optimization feature enables customers to shrink the die size beyond a human’s design potential. As a result, Cadence Cerebrus, when coupled with the broader Cadence digital product portfolio, provides a breakthrough engineering benefit with the industry’s most advanced digital full flow, from synthesis through implementation and signoff.

“We’re always looking for new ways to empower our customers to be more productive, and Cadence Cerebrus minimizes manual work through its AI capabilities so design engineers can focus on more critical projects,” said Dr. Chin-Chi Teng, senior vice president and general manager, Digital & Signoff Group at Cadence. “We launched Cadence Cerebrus less than a year ago, and it’s been remarkable to see how quickly our customers got up and running and started realizing the full potential of the product. Customers like MediaTek and Renesas have seen such positive PPA and productivity results that they’ve now adopted the tool widely for production flows.”

MediaTek Production Adoption

MediaTek is a leading fabless semiconductor company whose products power more than 2 billion connected devices across mobile, smart home, connectivity and AIoT products a year.

“At MediaTek, we are resolute in delivering optimal PPA, making the Cadence Cerebrus AI-based solution the most logical choice for our latest, advanced-node projects,” said Harrison Hsieh, senior general manager of Silicon Product Development at MediaTek. “On an SoC block, the Cadence Cerebrus floorplan optimization feature shrunk the die area by 5% and reduced power by more than 6%. After experiencing the compounded benefits of improved productivity, better PPA and ease of integration into the MediaTek CAD flow, we’ve deployed Cadence Cerebrus in our production flows.”

Renesas Production Adoption

Renesas is a leading provider of microcontrollers, analog and power devices to the automotive, industrial, infrastructure and IoT industries.

“We needed automation methodologies that improve PPA across a variety of nodes and design types,” said Toshinori Inoshita, vice president of the shared R&D EDA division at Renesas Electronics Corporation. “By deploying and optimizing Cadence Cerebrus to fit all our unique needs, we’ve had many notable design wins already. On an advanced-node CPU design, we experienced better performance with a 75% improvement in total negative slack (TNS). In addition, Cadence Cerebrus slashed the leakage power on a critical MCU design. We expect to further improve performance and productivity and reduce time to tapeout with Cadence Cerebrus.”

Share




Suggested Items

Kirigami Inspires New Method for Wearable Sensors

10/22/2019 | University of Illinois
As wearable sensors become more prevalent, the need for a material resistant to damage from the stress and strains of the human body’s natural movement becomes ever more crucial. To that end, researchers at the University of Illinois at Urbana-Champaign have developed a method of adopting kirigami architectures to help materials become more strain tolerant and more adaptable to movement.

Worldwide Semiconductor Equipment Billings at $13.3 Billion in 2Q19; Down 20%

09/12/2019 | SEMI
Worldwide semiconductor manufacturing equipment billings reached $13.3 billion in the second quarter of 2019, down 20% from the same quarter of 2018 and 3% from than the previous quarter.

Designing Chips for Real Time Machine Learning

04/01/2019 | DARPA
DARPA’s Real Time Machine Learning (RTML) program seeks to reduce the design costs associated with developing ASICs tailored for emerging ML applications by developing a means of automatically generating novel chip designs based on ML frameworks.



Copyright © 2022 I-Connect007. All rights reserved.