Cadence Tensilica Xtensa Processors Address Automotive Functional Safety Requirements

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Cadence Design Systems, Inc. announced that SGS-TÜV Saar has independently certified that Cadence® Tensilica® Xtensa® processors with FlexLock capability meet the ISO 26262:2018 standard to ASIL-D, the highest level possible under the Automotive Safety Integrity Level rating. The functional safety certification spans from base microcontroller to high-performance DSP, each with a configuration option for FlexLock to provide increased random fault protection and developed following a robust safety process to protect against systematic faults. Tensilica Xtensa processors with FlexLock are well suited for the automotive market and tailored for AI, vision, radar, lidar, audio, vehicle-to-everything (V2X), and control applications.

“Cadence Tensilica FlexLock processors optimized for automotive applications are among the first in the industry to achieve full compliance with ASIL-D functional safety standards,” said Wolfgang Ruf, head of functional safety for semiconductors at SGS-TÜV Saar. “Certification to our comprehensive assessment in accordance with the ISO 26262:2018 standard for ASIL-D systematic and random fault avoidance is a testament to the high functional safety quality of Cadence’s IP. SoC designers are assured that their designs using functional safety-certified Tensilica processor IP can achieve compliance with the automotive industry’s stringent safety-critical requirements.”

Key to ASIL-D compliance is the new FlexLock capability, which adds lockstep support to the flexible and extensible Xtensa processor architecture. Lockstep is a proven method for increasing safety in software execution by providing redundancy of the core logic at the hardware level. Not only does it provide the support needed to achieve ASIL-D certification, but FlexLock also gives design teams the ability to accommodate two cores running independently in ASIL-B solutions. In addition, the FlexLock solution allows the option of running local memories and caches of two cores in lockstep, achieving even greater levels of protection against memory faults.

“Innovation in functional safety features will continue to be critical in meeting the emerging trends and requirements of the automotive industry,” said Robert Dunnigan, ADAS MCU program manager at NXP. “We are pleased that Cadence is adding important functional safety mechanisms such as its FlexLock dual-core lockstep capability to its Tensilica IP product line.”

“Current trends in the automotive industry demand higher levels of functional safety,” said Hongquan Liu, senior marketing director at Calterah. “With the addition of the FlexLock dual-core lockstep capability, Cadence is demonstrating its commitment to meeting the needs of its customers with the most critical functional safety requirements.”

“Higher levels of autonomy require more intelligent computing at the edge in automotive applications, which is driving the need for higher levels of functional safety,” said Larry Przywara, senior group director, Tensilica marketing at Cadence. “With the introduction of FlexLock capability, users of Tensilica controllers and DSPs can achieve the highest level of certification, ASIL-D, and the protection it brings against random hardware faults. Designers choosing Tensilica IP to accelerate their ADAS, radar, lidar, V2X and vision processing can do so with the confidence that they can meet their customers’ functional safety requirements.”

As with other Xtensa processors, the ASIL-D certified cores can be customized using the Tensilica Instruction Extension (TIE) language. This allows the IP to be optimized for the specific application, combining the right level of performance with the highest levels of safety. Available today, the Tensilica Xtensa processors with FlexLock capability enable SoC design excellence in support of Cadence’s Intelligent System Design™ strategy. 



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